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Espressif Systems /ESP32-S2 /SENS /SAR_DAC_CTRL1

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Interpret as SAR_DAC_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SW_FSTEP0 (SW_TONE_EN)SW_TONE_EN 0DEBUG_BIT_SEL 0 (DAC_DIG_FORCE)DAC_DIG_FORCE 0 (DAC_CLK_FORCE_LOW)DAC_CLK_FORCE_LOW 0 (DAC_CLK_FORCE_HIGH)DAC_CLK_FORCE_HIGH 0 (DAC_CLK_INV)DAC_CLK_INV 0 (DAC_RESET)DAC_RESET 0 (DAC_CLKGATE_EN)DAC_CLKGATE_EN

Description

DAC control

Fields

SW_FSTEP

Frequency step for CW generator can be used to adjust the frequency.
SW_TONE_EN

0: disable CW generator. 1: enable CW generator.
DEBUG_BIT_SEL
DAC_DIG_FORCE

0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA.
DAC_CLK_FORCE_LOW

1: force PDAC_CLK to low
DAC_CLK_FORCE_HIGH

1: force PDAC_CLK to high
DAC_CLK_INV

1: invert PDAC_CLK.
DAC_RESET

Reset DAC by software.
DAC_CLKGATE_EN

DAC clock gate enable bit.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd